While the storage capacity of a semiconductor memory device as represented by a DRAM (Dynamic Random Access Memory) increases year after year along the progress of microfabrication techniques, the number of defective memory cells included per one chip also increases as miniaturization is proceeded. These defective memory cells are usually replaced by redundant memory cells, thereby relieving defective addresses.
In general, defective addresses are stored in a fuse circuit which includes plural program fuses. When an access to the defective addresses is requested, the fuse circuit controls to carry out a replacement access to not the defective memory cells but the redundant memory cells. These defective addresses are detected in a selection test carried out in a wafer state. The defective addresses are stored in the program fuses by irradiating a laser beam.
However, even after the addresses are replaced, defective bits are sometimes sporadically found due to heat stress during the packaging. When the defective bits are found after the packaging, the addresses cannot be replaced any more by irradiating a laser beam. Therefore, the chip needs to be handled as a defective product.
To solve the above problem, there has been proposed a method of providing a defect relief circuit capable of relieving a small number of defective bits that are found after the packaging, in addition to the address replacement by irradiating a laser beam. In this case, as a circuit which stores the defective addresses, an electrically writable nonvolatile memory circuit is used, instead of the fuse circuit which requires the irradiation of a laser beam. For this memory circuit, what is called an “antifuse circuit” using dielectric breakdown of an oxide film can be used (see Japanese Patent Application Laid-open No. 2006-108394).
The number of defective bits found after the packaging is extremely smaller than the number of defective bits found in the selection test. Therefore, it is desirable to replace the defective bits in a bit unit, not in a word line unit or a bit line unit. Accordingly, when a memory cell array is divided into plural banks, for example, several defect relief circuits can be provided for each bank. In this case, a defective-address storing circuit that stores a defective address and a comparing circuit that compares an access-requested address with the defective address can be provided for each bank.
However, the defective-address storing circuit that stores the defective address has a relatively large occupied area on the chip. Therefore, when the defective-address storing circuit is allocated to each bank, the chip area increases. Further, as described above, the number of defective bits found after the packaging is very small, and therefore, defects are not found in most of the banks. Consequently, the method of allocating a defective-address storing circuit for each bank has a problem of having only a small advantage for the increase of area.